In scaled technologies, the increasing levels of integration and process variation on minimum-sized devices in memory cells makes it challenging to maintain memory cell stability and write margin concurrently. Write margin can be enhanced by collapsing the power supply to the memory cell during write operation. In such a method, power supply voltage coupled to memory cells is reduced to weaken the strength of p-type transistors of the written memory cell to enhance write margin.
However, in partially selected cells along a column of memory cells, which are being written to, the state of the memory cells is maintained during the power supply collapse operation. The retention characteristics of these partially selected memory cells sets constraints on the duration and depth of power supply collapse, and are a technology sensitive metric that is difficult to predict at design time during technology development.
Currently, known methods of power supply collapse significantly increase Vcc-Vss cross-over current (current from power supply to ground), which is an impediment for low power designs. In low frequency cases where the collapsed voltage may need to stay at the suppressed level for an extended time, this cross-over current can increase the overall write power consumption by up to 2× in SRAMs (Static Random Access Memories).